LOW POWER DSP ARCHITECTURE FOR WIRELESS SENSOR NODES USING DVFS ALGORITHM

Abstract

Author(s): KASTHURI DEVI.R, MANIRAJ KUMAR.P

The trend of smaller, portable and more capable electronic devices gives rise to a number of significant design and implementation problems of which the limited energy supply is the most determining factors. All these issues are jointly present in the field of Wireless Sensor Networks which is consequently a suitable context for research opportunities. Radio communication has highest energy consumption. To reduce the energy and power parallel prefix technique is used. This base paper describes the design and implementation of newly proposed folded tree architecture. Folded tree architecture has two phases. They are trunk and twig phase. The power is reduced to compare to the existing methods. For further performance improvement Dynamic Voltage Frequency Scaling concept introduced along with Digital Signal processor architecture. This paper is on a low-power real-time scheduler integrated into a common Linux is operating system. The low power schedule aims at reducing energy consumption in a system and uses Dynamic Voltage and Frequency Scaling to achieve its goal. The major advantage of Dynamic Voltage and Frequency Scaling is the output frequency, phase and amplitude can be precise and also rapidly manipulated under the control of a DSP. These combined characteristics have made this technology popular in military, radar and communication systems. The digital circuits used to implement signal processing functions do not suffer the effects of thermal drifts aging and component variations associated with their analog counterpart.